The present disclosure relates to the field of electronic systems and more particularly, to a method and a system for converting an analog signal to a digital signal.
An Analog-to-Digital Converter (ADC) is a prerequisite for most digital signal processing. Most signals are analog by nature and have to be converted to digital format for a further digital signal processing. For example in multi-mode transceiver systems but also in a lot of other applications, portable/battery powered instruments, industrial controls and data/signal acquisition, analog-to-digital conversion (ADC) is an important part of the power budget and should be optimized, both on the system level (by determining the optimum combination of analog baseband signal processing and ADC speed and resolution) and on the building block level by making an ADC with the best Figure of Merit (FoM). This FoM is determined as
  FoM  =      P                  2        ENOB            ·              F        sample            and represents the energy used per conversion step. (P: power in W, Fsample: sample rate in 1/s, ENOB stands for the Effective Number of Bits.) State-of-the-Art ADCs achieve a FoM below 1 pJ (0.5 to 1 pJ/conversion step).
On top of that, scalability is also a major issue for multi-mode transceivers and an ADC topology is desirable that can scale its power consumption linearly with the requirements on accuracy and speed in order not to waste power in operating modes with lower requirements. State of the art solutions are not satisfactory. Some topologies offer scalable performance, but at the cost of a worse FoM.
A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete representation via a binary search through all possible quantization levels. A common form of analog to digital converter uses an array of capacitors that are controlled by successive approximation register (SAR) logic. A comparator is used to perform successive comparisons of the input voltage to a test voltage. The SAR ADC is low in cost and consumes low operating power.
A conventional SAR ADC with a sample-and-hold circuit is depicted in FIG. 1. The analog signal Vin enters the sample-and-hold (S/H) circuit where the signal simply is sampled and held to provide a buffer for the ADC. Vin is compared in the comparator to Vref. The digital comparison result goes to the SAR. The SAR adjusts the digital control signals in order to narrow the compared voltages. An adjusted digital signal is output to a digital-to-analog converter (DAC). This signal is converted to an adjusted Vref, which is compared to Vin in the comparator. A number of examples can be found in the prior art as for example in US2006/0187106.
Since comparator speeds up to 1 GHz can easily be achieved in deep-submicron technologies, successive approximation ADCs are feasible for conversion speeds and accuracies in the range of 8-10 bits and 10-50 MHz. The most used topologies are capacitive-based, also known as charge redistribution SAR ADC. A number of systems are based on this principle, for example that disclosed in Publication No. US2003/0063026. These topologies have a lot of disadvantages. Since the number of conversion bits is determined sequentially, each bit of resolution requires a conversion operation. As a result, the conversion time tends to become unacceptably long for high-speed and high-resolution applications. A typical ADC employs a switching capacitor as the DAC; these devices tend to exhibit the traits of change injection during switching, as well as embodying long settling times. To achieve fast settling, opamps with large biasing currents are used, which makes it impossible to achieve a good FoM. As these opamps need constant biasing, power cannot be scaled linearly with conversion speed.
A typical capacitive SAR ADC needs a fast opamp at the input to settle fast to the required output voltage.
The paper “Clock-feedthrough compensated switched-capacitor circuits” (Ogawa et al., Proceedings Int'l Symposium on Circuits and Systems (ISCAS), 1992, pp. 1195-1198) gives a solution to the clock-feedthrough effect that typically occurs in switched-capacitor circuits. The proposed switched-capacitor circuits comprise opamps with large biasing currents. As these opamps need constant biasing, power cannot be scaled linearly with conversion speed. Moreover, such opamps with large biasing currents do not allow achieving a good Figure of Merit.
US2006/0208935-A1 relates to an A/D converter comprising several conversion engines collaborating together to determine during a single trial a plurality of bits. It also shows a single switched capacitor ADC conversion engine, comparable to a classical SAR ADC where a capacitor bank can be connected to an input, a reference voltage and ground.